The ``Processor ADC and Sensor Integrated Circuit'' (PASIC) as the name suggests consists of a sensor array, A/D converters, and processors [Chen et al. 90b, Chen et al. 90a, Chen et al. 90c]. Each column has its own ADC and processor. The architecture of PASIC is shown in Figure 2.12.
A/D conversion is performed in parallel for each selected row. The counter starts from zero and counts up. Whenever the voltage from DAC reaches output voltage of a cell, the counter value is stored in the associated register.
The processing elements consist of three parts, one bi-directional parallel shift register, one ALU, and a memory. These modules communicate to each other through a 1-bit bus. Variaous operation between these modules occur on single bits at a time. Therefore each instruction requires several clock cycles to complete.
Using this bit-serial processor approach several simple image processing operations, such as binary image dilation and erosion, and more complicated operations, such as convolution and histogram collection, have been implemented.
The sensor array in PASIC has 128 
128 photodetectors. The chip
occupies an area of about 9mm 11mm.
