Fixed pattern noise (FPN) [Fry et al. 70] is one of the main disadvantages of CMOS imagers in comparison with CCD imagers. In a CCD imager charge is transferred between neighboring CCD elements with a high charge transfer efficiency. The amount of the charge collected by a pixel in a CCD imager is also not heavily dependent on the parameters of the device. However, in CMOS imagers the charge at a pixel passes through CMOS circuits which in addition to adding some systematic nonlinearity have a high mismatch.
In a simplest method cancelling FPN can be performed by on-chip or off-chip storage of the offset values, obtained by reading the output of the photocircuits while they are reset. This method, however, requires a large amount of memory for storing the whole offset information.
Correlated double sampling (CDS) is another method in which during the pixel read-out cycle, two samples are taken. One when the pixel is still in the reset state, and one when the charge has been transferred to the read-out node. The two values are then used as differential signals in further stages, such as programmable gain amplifiers (PGA) or ADC. The CDS circuit is shown in Figure 7.25. Although CDS reduces the fixed pattern noise to a large extent, a component of the FPN due to mismatch in the CDS circuits at each column introduces column-FPN. This noise can be reduced by using a similar concept.
It should be noted that this CDS circuit can be completely effective, only if the FPN is intensity independent, if the circuits (for example the source follower stage at each pixel) are linear, and the mismatch only has an offset component. In reality these assumptions are not true and more elaborate CDS circuits which can compensate for gain mismatch and nonlinearity in the circuits are required.
Figure 7.25: Schematic diagram of the correlated double sampling circuit.
There is one such circuit for every column.