The optical neurochips and the retina designed at Mitsubishi Electric Co. are based on optical interconnection and processing of the image using special GaAs photodetectors and light emitting diodes (LED) integrated on the same chip [Nitta et al. 92, Nitta et al. 93a, Nitta et al. 93c, Nitta et al. 93b, Nitta et al. 95, Lange et al. 93, Lange et al. 95, Lange et al. 94, Ohta et al. 89, Oita et al. 94, Oita et al. 93]. The chips do not implement any particular vision processing algorithm. However, they utilize interesting features of GaAs variable sensitivity photodetectors (VSPD) and LEDs and combine them in a single chip. Using integrated VSPD and LEDs the optical crosstalk between adjacent channels is significantly reduced, with respect to previously reported multichip optical neurochips.
The photodetectors are designed using metal-semiconductor-metal (MSM) structures. By applying positive or negative voltage to the metal electrodes of the detector its sensitivity can be varied correspondingly and positive or negative output current be obtained. The photodetectors also show an analog memory behavior, which is very useful for synaptic weight storage in the implementation of neural networks.
In the optical neurochips the inputs are an array of analog signals controlling the intensity of light emitting diodes underneath the VSPD elements. Therefore, the photodetectors modulate the internal image with the control voltage.
The GaAs retina chips described in [Lange et al. 93, Lange et al. 95, Lange et al. 94] are based on devices and structures used in the optical neurochips. The input image is detected by VSPDs. The image is then vector multiplied by the photodetector control voltage. The vector multiplication is performed by: selecting the desired pixels, applying the proper kernel (control voltages) to these pixels, and reading the output. The output currents of the VSPD elements in one column are added together. The architecture of the retina chip is shown in Figure 5.1.
Several neurochips with different sizes have been fabricated. Two
retinas with 64 
64 pixels (with a cell size of 160 
) and
128 128 pixels (with a cell size of 80 ) have also been
designed and fabricated. The larger chip fits in a
14.3mm 14.3mm die. Some image processing operations, such as
edge detection, feature extraction, and spatial smoothing have been
demonstrated using these chips.
Figure: Lange et al.'s GaAs retina.