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Mahowald and Delbrück's stereo matching chips

 

In  [Mahowald and Delbrück 89] Mahowald and Delbrück present two stereo matching chips which use static and dynamic features of image. Both chips use Marr/Poggio's algorithm for stereo matching of two right and left image planes [Marr and Poggio 76], and compute disparities on nine disparity planes. The chip architecture is shown in Figure 2.4, which illustrates only three disparity planes. In the first chip, retina elements are a 1D version of the 2D Mahowald-Mead's retina described in Section 2.2 [Mahowald 94a]. The outputs of the two right and left retinas are multiplied together using a four-quadrant Gilbert multiplier and provide input for the correlator. In the second chip the retina elements are not connected together and are based on the time-derivative pixel circuit, which is capacitively coupled to a rectifier. The block diagrams of the correlator input circuitry in both chips are shown in Figure 2.5.

The correlation circuitry after node ``X'' in the correlator box is similar in both chips and is shown in Figure 2.6. The final output of the chips are the voltages at the Output nodes of the correlator circuits.

The chips have 40 pixels in a 2 tex2html_wrap_inline7217 m CMOS process. Experimental results are provided in [Mahowald and Delbrück 89].

   figure229
Figure 2.4: Architecture of Mahowald-Delbrück's stereo matching chip. Excitation in a disparity plane is done by the resistive elements. The inhibitory connections from neighboring disparity planes are not shown.

   figure237
Figure 2.5: Schematic diagram of correlator input for a) the static input image chip, and b) the dynamic input image chip.

   figure245
Figure 2.6: Simplified circuit of the correlator.


Tobi Delbr\"{u}ck's home page

To obtain a PS file about the design of this chip (229K)

A file about the design of time-derivative detectors (69K)



next up previous contents
Next: Bernard et al.'s Boolean artificial Up: Spatial Image Processing Vision Previous: Mead's adaptive retina

Alireza Moini,
Centre for High Performance Integrated Technologies and Systems (CHIPTEC),
Adelaide, SA 5005,
March 1997