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Horiuchi et al.'s delay line-based motion detection chip

 

This motion detection chip is based on an extended delay-based motion detection algorithm [Horiuchi et al. 91]. The signal from each photoreceptor is passed through a firing neuron which fires on the detection of a specific feature (the rising edge of the signal from photodetectors). The outputs of the firing neurons are then passed through a series of delay lines, and are compared with the delayed signals from neighboring cells. The signals from neighboring photoreceptors are delayed in opposite directions as shown in Figure 3.18. When two contiguous neurons fire, their output signals race through the delay lines towards each other and meet somewhere on the line, where a large signal will be created by the correlating circuits (the circles in Figure 3.18). The meeting point will be detected by the winner-take-all circuit. If the neurons fire at the same time, the signals will meet in the middle of the delay line. Positive or negative motion can be detected by looking at the displacement with respect to the middle point.

Although the method seems promising as a multi-velocity (compared with Delbrück's single velocity tuned motion detector described in Section 3.8), due to the aggregation of the output signals of the correlators, it can only detect a uniform optic-flow across the 1D array. In fact it can only report a single global velocity vector, and is not able to locate multiple objects moving at the same or different velocities.

The fabricated chip contains 28 photodetectors.

   figure906
Figure: Architecture of Horiuchi et al.s motion detection chip.


Tim Horiuchi's home page

To obtain a PS file about the design of this chip (64 K)

To obtain a PS file about the design of this chip (64 K)

A file about the design of the WTA circuit used in this motion detection chip (73K)



next up previous contents
Next: Chong et al.'s change detector Up: Spatio-Temporal Image Processing Vision Previous: Dron's multi-scale veto CCD

Alireza Moini,
Centre for High Performance Integrated Technologies and Systems (CHIPTEC),
Adelaide, SA 5005,
March 1997