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DeWeerth's Localization and Centroid Computation Chip

 

DeWeerth has implemented a centroid detection chip [Deweerth 92] based on an aggregation network shown in Figure 2.20. Using this circuit an output current of the form

displaymath7328

is obtained. In order to use this circuit for spatial centroid detection, a spatially-sweeping reference voltage is produced at one input of the differential pairs. This is simply done by a resistive voltage divider with its ends connected to reference voltages, tex2html_wrap_inline7330 and tex2html_wrap_inline7332 . The other input of the differential pairs are all connected together and connected to the output of the circuit. Photocurrents are presented as the biasing current of the differential pairs. In the actual implementation described in [Deweerth 92] the input transistors of the differential pairs are realized using bipolar transistors to reduce the effects of device mismatch. Polysilicon resistors have been used for the voltage divider.

Obviously, the nonlinearity of the tanh function affects the operation, if proper assumptions or constraints are not made. It is reasonably assumed that the voltage difference across each resistor, tex2html_wrap_inline7334 , is very small. This can easily be satisfied by a choice of reference voltages. An analysis for a simple case of constant background illumination and constant-width-and-intensity object is given in [Deweerth 92].

The 160 tex2html_wrap_inline7232 160 array of this centroid detection chip has been realized in a 2 tex2html_wrap_inline7217 m BiCMOS process in an area of 6.8mm tex2html_wrap_inline7232 6.9mm.

   figure490
Figure 2.20: DeWeerth's spatial aggregation circuit.

   figure498
Figure 2.21: DeWeerth's spatial centroid detection circuit.


next up previous contents
Next: Ward & Syrzycki's Receptive Up: Spatial Image Processing Vision Previous: Harris et al.'s Resistive

Alireza Moini,
Centre for High Performance Integrated Technologies and Systems (CHIPTEC),
Adelaide, SA 5005,
March 1997