VHDL/Verilog interactive simulator

This is an online interactive VHDL/Verilog simulator based on GHDL for VHDL and Icarus Verilog for Verilog. It uses some of the inputs and outputs found in the terasIC DE10 board (Altera-Intel FPGA evaluation board) and most DExx evaluation boards. Try the included examples or drag and drop your own VHDL or Verilog file into this window. Your custom VHDL or Verilog file should have the same entity or module interface as shown in the default examples.

These are the inputs and outputs available for your VHDL/Verilog code:

• clk500Hz: 1x 500Hz clock, which is "hardwired" to an internal 500 Hz clock. It resembles the 50 MHz clock of the DE10 board, though running slower for online realtime simulation performance reasons.
• sw[9:0]: 10x input switches.
• key[3:0]: 4x input keys (active low).
• led[9:0]: 10x output LEDs (active high).
• hex1[6:0], hex0[6:0]: 14x outputs for the two 7-segment displays (active low).