Mismatch has been the worst limiting factor in designing analog VLSI systems, including vision chips. Mismatch can be regarded as a spatial noise spread over the surface of a vision chip. The main effects of mismatch on system performance are: dynamic range reduction due to increased spatial noise level, precision limitation, area increase, and power dissipation increase. When designing circuits all these parameters should be traded off against each other. In the absence of mismatch minimum size transistors, with minimum area and minimum capacitances could be used. As a result power dissipation could also be reduced as the loads in the circuit are decreased.
Mismatch in CMOS circuits stems from three main sources
[Bastos et al. 95, Pavasovic et al. 94a, Pavasovic et al. 94b, Steyaert et al. 94, Forti and Wright 94]. The first one is the physical variation
of device dimensions. For example the variation of the gate length
and width in a 2 
m process can be up to several 0.1 m. The
only way to reduce the effect of this source of mismatch is to use
large devices such that the effect of variation which often occurs at
the edges of the device can be neglected.
The other source of mismatch is the metallurgical variation of device parameters, which mainly includes the variation of doping densities in the semiconductor. This type of mismatch can also be reduced by using large size transistors.
The third source of mismatch is from some electronic parameters of the device. For example, the trapped charges in the gate oxide, or the surface states in a MOS transistor can change the threshold voltage of the device.
From these source the third one is more prevalent in MOS transistors, and it is concluded that the devices which are affected by the surface properties of the semiconductor will have more mismatch than those which mainly depend on the properties of the semiconductor away from the surface. This is in fact the main reason why BJTs and junction diodes have less mismatch than MOS devices.
Mismatch in MOS devices depends on the following parameters:
) is almost constant, but
as the transistor enters the above-threshold region it decreases at
an exponential rate.
In general finding the total mismatch of a network requires special
treatment of that network, and if the circuits operate at different
current levels and have different dimensions the solution would
require nonlinear analysis of the network. In the special case of
translinear circuits, which have been widely used in the design of
many vision chips, a simplified analysis shows that mismatch in the
output is proportional to 
, where N is number of transistors
in the circuit. MOS translinear circuits all operate in subthreshold
region, and therefore have an almost independent mismatch from current
levels. However, one should notice that in subthreshold the amount of
mismatch can be higher by more than one order of magnitude, and
therefore subthreshold circuits should be avoided as much as possible
if one is concerned about mismatch.
Circuit simulation tools, such as HSPICE, can be used to find the mismatch by applying constant inputs to the network and assuming mismatch levels for the threshold voltage and transconductance (through principle component analysis it is found that mismatch can be associated with these two parameters only) of the individual transistors in the network.