Logica Programable, Criterios de Selecci'on

Fernando Pardo, Jose A. Boluda, Rafael Martinez y Carlos Perez

Abstract

The complexity of digital systems has increased so much in the last years that new electronic design techniques are needed to face this work. Due to the heightening popularity of field-programmable gate arrays and high complexity programmable logic devices (FPGAs and CPLDs, respectively), the curtain is quickly drawing closed on gate arrays as a design solution for many low-to-moderate-complexity digital systems. PLDs have progressed from simple programmable-array logic (PAL) elements, to more complex CPLDs, to the most complex PLDs-FPGAs. These field-programmable logic chips have evolved over the last 15 years from simple chips that could replace a dozen or so gates to complex arrays that compete head-to-head with low-density (sub-20,000-gate) arrays. Gate densities have surged from about 300 to over 22,000 gates per chip, while operating speeds soared from 20 to 100 MHz. Complexities have also snowballed to the point where original 20-pin packages provide less than 1/10 the connectivity and 1/1000 the density of complex 232-pin FPGAs now available.

Trying to categorise the various PLD offerings can be very confusing. At first glance, it is not clear where simply PLDs stop and complex PLDs begin, and where FPGAs leave off and FPGAs begin. The selection of a device for a specific application is not easy, the dizzying array of architectural options makes selection difficult. Add to that the mostly exaggerated claims of high gate counts and short pin-to-pin delays on FPGAs and CPLDs, and selecting the best match for the application borders on the hopeless. Programming options often depends on the programming scheme used. Today's programming schemes give users four choices: ultraviolet-erasable and electrically programmable memory cells (UV EPROM), electrically-erasable and reprogrammable memory cells (EEPROM), one-time programmable antifuses (or one-time programmable programmable EPROM) and SRAM-based programming structures.

Three devices were analysed, Altera CPLDs (UV EPROM), Xilinx FPGAs (SRAM based), and Texas Instruments FPGAs (Antifuses EPROM). These devices were elected because they were the most representative and popular of each programming scheme. The analysis shows that reprogrammable devices are better for limited number of chips productions, while one-time programmable devices are more suitable for moderate-high number of chips productions due to their lower price. FPGAs arise as the more complex devices, where more devices can fit. However PLDs allow higher clock frequencies, fixed pin-to-pin delays, and easier programming at higher clock speed.